Cadence tutorial -CMOS NAND gate schematic, layout design and Physical Verification(Assura tutorial)
In this cadence (IC6.1.5) tutorial, I used cadence 90nm Gpdk technology file to schematic design as well as layout design, For physical verification of layout, i had used cadence tool Assura (Physical verification tool). Some Important links 1. Assura installation procedure. 2. Cadence 90nm Gpdk setup 3. cshrc setup This article was gathered automatically by … Read more
